devices incorporated video imaging products 1 lf48212 12 x 12-bit alpha mixer 08/16/2000Clds.48212-f q q q q q 50 mhz data and computation rate q q q q q twos complement or unsigned operands q q q q q on-board programmable delay stages q q q q q programmable output rounding q q q q q replaces harris hsp48212 q q q q q package styles available: ? 68-pin plcc, j-lead ? 64-pin pqfp features description lf48212 12 x 12-bit alpha mixer devices incorporated the lf48212 is a high-speed video alpha mixer capable of mixing video signals at real-time video rates. it takes two 12-bit video signals and mixes them together using an alpha mix factor. alpha determines the weighting that each video signal receives during the mix operation. the input video data can be in either unsigned or twos complement format, but both inputs must be in the same format. independently con- trolled programmable delay stages are provided for the input and control signals to allow for allignment of input data if necessary. the delay stages can be programmed to have from 0 to 7 delays. the 13-bit output of the alpha mixer is registered with three-state drivers and may be rounded to 8, 10, 12, or 13-bits. lf48212 b lock d iagram dina 11-0 a 11-0 dinb 11-0 format format 0-7 a 1.0 C a 0-7 0-7 adjust format dout 12-0 0-7 0-7 tc rnd 1-0 delay control register bypass del ld clk mixen oe note: numbers in registers indicate number of pipeline delays. 12 12 12 13 2 15 4 4
devices incorporated lf48212 12 x 12-bit alpha mixer 2 video imaging products 08/16/2000Clds.48212-f signal definitions power v cc and gnd +5 v power supply. all pins must be connected. clock clk master clock the rising edge of clk strobes all enabled registers except for the delay control register. inputs dina 11-0 pixel data input a dina 11-0 is one of the 12-bit regis- tered data input ports. data is latched on the rising edge of clk. dinb 11-0 pixel data input b dinb 11-0 is the other 12-bit registered data input port. data is latched on the rising edge of clk. a 11-0 alpha mix input a 11-0 determines the weighting applied to the data input signals before being mixed together. dina 11-0 and dinb 11-0 receive weightings of a and 1.0 C a respectively. a 11-0 is unsigned and restricted to the range of 0 to 1.0. figure 1 shows the data format for a 11-0 . if a value greater than 1.0 is latched into the alpha mix input, internal circuitry will force the value to be equal to 1.0. data is latched on the rising edge of clk. del delay data input del is used to load the delay control register. the delay control register contains a 15-bit value which deter- mines the number of delay stages added to the input and control signals. the 15-bit data value is loaded serially into the delay control register using del and ld. data present on del is latched on the rising edge of ld. f igure 1. a lpha m ix i nput f ormat 11 10 9 6 5 4 87 3210 2 0 2 C1 2 C2 2 C5 2 C6 2 C7 2 C3 2 C4 2 C8 2 C9 2 C10 2 C11 outputs dout 12-0 data output dout 12-0 is the 13-bit registered data output port. controls tc data format control tc determines if the input data is in unsigned or twos complement format. if tc is low, the data is in twos complement format. if tc is high, the data is in unsigned format. data present on tc is latched on the rising edge of clk. tc only affects the data that is being latched into the lf48212. changing tc does not affect internal data already in the pipeline. mixen alpha mix input enable when high, data on a 11-0 is latched into the lf48212 on the rising edge of clk. when low, data on a 11-0 is not latched and the last value loaded is held as the alpha mix value. ld load strobe the rising edge of ld latches the data on del into the delay control register. bypass bypass delay stage control the bypass control is used to bypass the internal programmable delay stages. when bypass is set high, the delay control register will automatically be loaded with a 0. this will set the number of program- mable delay stages to zero for all input and control signals. when bypass is low, the desired number of delay stages can be set by loading rnd 1-0 rounding format 00 round to 8-bits 01 round to 10-bits 10 round to 12-bits 11 round to 13-bits t able 1. o utput r ounding the delay control register with the appropriate value. note that this signal is not intended to change during active operation of the lf48212. rnd 1-0 output rounding control rnd 1-0 determines how the output of the lf48212 is rounded. the output may be rounded to 8, 10, 12, or 13-bits. table 1 lists the different rounding possibilities and the associated value for rnd 1-0 . rounding is accom- plished by adding a 1 to the bit to the right of what will become the least significant bit. then the bit that had the 1 added to it and all bits to the right of it are set to 0. data present on rnd 1-0 is latched on the rising edge of clk. when rnd 1-0 is latched in, it only applies to the video input data latched in at the same time. changing rnd 1-0 does not affect the rounding format for internal data already in the pipeline. oe output enable when oe is low, dout 12-0 is enabled for output. when oe is high, dout 12-0 is placed in a high- impedance state.
devices incorporated video imaging products 3 lf48212 12 x 12-bit alpha mixer 08/16/2000Clds.48212-f functional description the two video signals to be mixed together are input to the lf48212 using dina 11-0 and dinb 11-0 . data present on dina 11-0 and dinb 11-0 is latched on the rising edge of clk. the input data may be in either unsigned or twos complement format, but both inputs must be in the same format. tc determines the format of the input data. when tc is high, the input data is in unsigned format. when tc is low, the input data is in twos complement format. tc is latched on the rising edge of clk and only affects the input data latched in at the same time. the data already in the pipeline is not affected when tc changes. dina 11-0 and dinb 11-0 are mixed together using an alpha mix factor ( a 11-0 ) as defined by the equation listed in figure 2. a 11-0 is unsigned and restricted to the range of 0 to 1.0. mixen controls the loading of alpha mix data. when mixen is high, data present on a 11-0 is latched on the rising edge of clk. when mixen is low, data present on a 11-0 is not latched and the last value loaded is held as the alpha mix value. it is possible to add extra delay stages to the input data and control signals by using the programmable delay stages. the 15-bit value (delay 14-0 ) stored in the delay control register determines the number of delay stages added. delay 14-0 is divided into 5 groups of 3-bits each. each 3-bit group contains the delay information for one of the input data or control signals. figure 3 shows the block diagram of the delay control register as well as a list of the input data and control signals that may be delayed and the delay signals that control them. the delay length can be pro- grammed to be from 0 to 7 stages. the delay length is set by loading the binary equivalent of the desired delay length into the appropriate 3-bit group. for example, to add four extra delay stages to dinb 11-0 , delay 5-3 should be set to 100. delay 14-0 is loaded serially into the delay control register using del and ld. delay 0 is the first value loaded and delay 14 is the last. data present on del is latched on the rising edge of ld. bypass is used to disable the pro- grammable delay stages. when bypass is high, the delay control register is automatically loaded with a 0. this sets all programmable delay stages to a length of zero. when bypass is low, the delay control register may be loaded to set the desired number of delay stages. note that bypass is not intended to change during active operation of the lf48212. the adjust stage of the lf48212 is used to maximize the precision of the output data. since a can never be larger than 1.0, the most significant bit of the internal summer output is not needed. the adjust stage takes the output of the internal summer and left shifts the data one bit position. this removes the msb of the internal summer output and provides one more bit of precision for the output data. the output data of the lf48212 may be rounded to 8, 10, 12, or 13-bits. rnd 1-0 determines how the output is rounded (see table 1). rnd 1-0 is latched on the rising edge of clk and only affects the input data latched in at the same time. the data already in the pipeline is not affected when rnd 1-0 changes. f igure 3. d elay c ontrol r egister b lock d iagram del ld dq dq dq delay 14 delay 13 delay 12 ld ld dq dq dq delay 11 delay 10 delay 9 ld ld dq dq dq delay 8 delay 7 delay 6 ld ld dq dq dq delay 5 delay 4 delay 3 ld ld dq dq dq delay 2 delay 1 delay 0 ld ld rnd 1-0 delay tc delay a 11-0 delay dinb 11-0 delay dina 11-0 delay f igure 2. o utput e quation output = a (dina) + (1 C a )dinb
devices incorporated lf48212 12 x 12-bit alpha mixer 4 video imaging products 08/16/2000Clds.48212-f o perating c onditions to meet specified electrical and switching characteristics mode temperature range (ambient) supply voltage active operation, commercial 0c to +70c 4.75 v v cc 5.25 v storage temperature ........................................................................................................... C65c to +150c operating ambient temperature ........................................................................................... C55c to +125c v cc supply voltage with respect to ground ............................................................................ C0.5 v to +7. 0v input signal with respect to ground ............................................................................... C0.5 v to v cc + 0.5 v signal applied to high impedance output ...................................................................... C0.5 v to v cc + 0.5 v output current into low outputs ................................................................................................ ............. 25 ma latchup current ................................................................................................................ ............... > 400 ma m aximum r atings above which useful life may be impaired (notes 1, 2, 3, 8) symbol parameter test condition min typ max unit v oh output high voltage v cc = min., i oh = C400 a 2.6 v v ol output low voltage v cc = min., i ol = 2.0 ma 0.4 v v ih input high voltage 2.0 v cc v v il input low voltage (note 3) 0.0 0.8 v i ix input current ground v in v cc (note 12) 10 a i oz output leakage current ground v out v cc (note 12) 10 a i cc1 v cc current, dynamic (notes 5, 6) 120 ma i cc2 v cc current, quiescent (note 7) 500 a c in input capacitance t a = 25c, f = 1 mhz 10 pf c out output capacitance t a = 25c, f = 1 mhz 10 pf e lectrical c haracteristics over operating conditions (note 4)
devices incorporated video imaging products 5 lf48212 12 x 12-bit alpha mixer 08/16/2000Clds.48212-f lf48212C 25 20 symbol parameter min max min max t cyc cycle time 25 20 t pw clock pulse width 10 10 t s input setup time 11 11 t h input hold time 0 0 t d output delay 14 14 t ena three-state output enable delay (note 11) 13 13 t dis three-state output disable delay (note 11) 13 13 c ommercial o perating r ange (0c to +70c) notes 9, 10 (ns) switching characteristics s witching w aveforms :d ata i/o clk t cyc t pw t pw dina 11-0 dinb 11-0 t s t h dout 12-0 a 11-0 t s t h controls* t s t h oe t d t dis t ena high impedance *includes mixen , tc , and rnd 1-0 .
devices incorporated lf48212 12 x 12-bit alpha mixer 6 video imaging products 08/16/2000Clds.48212-f lf48212C 25 20 symbol parameter min max min max t lc ld cycle time 25 20 t lpw ld pulse width 10 10 t ds del setup time 12 12 t dh del hold time 0 0 c ommercial o perating r ange (0c to +70c) notes 9, 10 (ns) s witching w aveforms :d elay c ontrol r egister d ata ld t lc t lpw t lpw del t ds t dh
devices incorporated video imaging products 7 lf48212 12 x 12-bit alpha mixer 08/16/2000Clds.48212-f 1. maximum ratings indicate stress specifications only. functional oper- ation of these products at values beyond those indicated in the operating condi- tions table is not implied. exposure to maximum rating conditions for ex- tended periods may affect reliability. 2. the products described by this spec- ification include internal circuitry de- signed to protect the chip from damag- ing substrate injection currents and ac- cumulations of static charge. neverthe- less, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values. 3. this device provides hard clamping of transient undershoot and overshoot. in- put levels below ground or above v cc will be clamped beginning at C0.6 v and v cc + 0.6 v. the device can withstand indefinite operation with inputs in the range of C0.5 v to +7.0 v. device opera- tion will not be adversely affected, how- ever, input current levels will be well in excess of 100 ma. 4. actual test conditions may vary from those designated but operation is guar- anteed as specified. 5. supply current for a given applica- tion can be accurately approximated by: where n = total number of device outputs c = capacitive load per output v = supply voltage f = clock frequency 6. tested with all outputs changing ev- ery cycle and no load, at a 40 mhz clock rate. 7. tested with all inputs within 0.1 v of v cc or ground, no load. 8. these parameters are guaranteed but not 100% tested. ncv f 4 2 notes 9. ac specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 v (except t dis test), and input levels of nominally 0 to 3.0 v. output loading may be a resistive divider which provides for specified i oh and i ol at an output voltage of v oh min and v ol max respectively. alternatively, a diode bridge with upper and lower current sources of i oh and i ol respectively, and a balancing voltage of 1.5 v may be used. parasitic capacitance is 30 pf minimum, and may be distributed. this device has high-speed outputs ca- pable of large instantaneous current pulses and fast turn-on/turn-off times. as a result, care must be exercised in the testing of this device. the following measures are recommended: a. a 0.1 f ceramic capacitor should be installed between v cc and ground leads as close to the device under test (dut) as possible. similar capacitors should be installed between device v cc and the tester common, and device ground and tester common. b. ground and v cc supply planes must be brought directly to the dut socket or contactor fingers. c. input voltages should be adjusted to compensate for inductive ground and v cc noise to maintain required dut input levels relative to the dut ground pin. 10. each parameter is shown as a min- imum or maximum value. input re- quirements are specified from the point of view of the external system driving the chip. setup time, for example, is specified as a minimum since the exter- nal system must supply at least that much time to meet the worst-case re- quirements of all parts. responses from the internal circuitry are specified from the point of view of the device. output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 11. for the t ena test, the transition is measured to the 1.5 v crossing point with datasheet loads. for the t dis test, the transition is measured to the 200mv level from the measured steady-state output voltage with 10ma loads. the balancing volt- age, v th , is set at 3.5 v for z-to-0 and 0-to-z tests, and set at 0 v for z- to-1 and 1-to-z tests. 12. these parameters are only tested at the high temperature extreme, which is the worst case for leakage current. s1 i oh i ol v th c l dut oe 0.2 v t dis t ena 0.2 v 1.5 v 1.5 v 3.5v vth 1 z 0 z z 1 z 0 1.5 v 1.5 v 0v vth v ol * v oh * v ol * v oh * measured v ol with i oh = C10ma and i ol = 10ma measured v oh with i oh = C10ma and i ol = 10ma f igure b. t hreshold l evels f igure a. o utput l oading c ircuit
devices incorporated lf48212 12 x 12-bit alpha mixer 8 video imaging products 08/16/2000Clds.48212-f plastic j-lead chip carrier (j2) lf48212jc25 LF48212JC20 ordering information 0c to +70c c ommercial s creening speed 25 ns 20 ns 68-pin 1 2 3 4 5 6 7 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 68 67 66 65 64 63 36 35 37 38 39 41 30 29 31 32 33 34 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 40 top view 8 96261 28 27 42 43 dinb 11 dinb 10 dinb 9 dinb 8 dinb 7 dinb 6 gnd dinb 5 nc dinb 4 dinb 3 dinb 2 dinb 1 dinb 0 rnd 1 rnd 0 del oe dout 12 dout 11 dout 10 dout 9 gnd dout 8 dout 7 nc dout 6 dout 5 v cc dout 4 dout 3 dout 2 dout 1 dout 0 ld tc dina 11 dina 10 dina 9 v cc dina 8 dina 7 nc dina 6 dina 5 dina 4 gnd dina 3 dina 2 dina 1 dina 0 clk mixen a 0 a 1 a 2 a 3 a 4 a 5 nc a 6 a 7 v cc a 8 a 9 a 10 a 11 bypass
devices incorporated video imaging products 9 lf48212 12 x 12-bit alpha mixer 08/16/2000Clds.48212-f plastic quad flatpack (q3) lf48212qc25 lf48212qc20 ordering information 0c to +70c c ommercial s creening speed 25 ns 20 ns 64-pin dinb 11 dinb 10 dinb 9 dinb 8 dinb 7 dinb 6 gnd dinb 5 dinb 4 dinb 3 dinb 2 dinb 1 dinb 0 rnd 1 rnd 0 del clk mixen a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 v cc a 8 a 9 a 10 a 11 bypass oe dout 12 dout 11 dout 10 dout 9 gnd dout 8 dout 7 dout 6 dout 5 v cc dout 4 dout 3 dout 2 dout 1 dout 0 ld tc dina 11 dina 10 dina 9 v cc dina 8 dina 7 dina 6 dina 5 dina 4 gnd dina 3 dina 2 dina 1 dina 0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
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